Parallel algorithms for VLSI circuit extraction

Parallel processing has recently become an extremely attractive and cost effective way of achieving orders of magnitude performance improvements in VLSI CAD applications. In this paper, we propose parallel algorithms to speed up the VLSI circuit extraction task. Given a VLSI layout as input, the problem of circuit extraction consists of determining the circuit connectivity and estimating the various electrical parameters such as the resistances of lines, capacitances of nodes, and dimensions of devices. Circuit extraction is a computationally intensive problem. The basic approach used in the parallel algorithms is the partitioning of a circuit into smaller regions, assigning each region to a processor and having the processors cooperate in performing the extraction procedures. We present a number of partitioning strategies that could be used. We have implemented the parallel algorithms on an Intel iPSC2 hypercube and an Encore 510 multimax shared memory multiprocessor. ADDRESS FOR CORRESPONDENCE P. Banerjee Computer Systems Group Coordinated Science Laboratory University of Illinois 1101 W. Springfield Av. Urbana, IL-61801 (217) 244-6564